资源列表
debug_module_wrapper
- 赛灵思FPGA开发板上调试模块的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board debug module' s VHDL source code, hardware design can be used as reference!
uart
- uart接口读写控制器，已经在fpga上测试通过-uart interface to read and write controller, has been tested by fpga
10BASET_TxD
- this the code for the 10base txd application-this is the code for the 10base txd application
music-player
- 实现音乐播放器设计，有音乐播放查表电路模块-finish the design of music player,it has the look-up circuit table module of music playing
MLAW_LINEAR_CONVERTER
- This a HDL implementation of G711 MLAW to LINEAR and vice versa converter. Uses very less resources. -This is a HDL implementation of G711 MLAW to LINEAR and vice versa converter. Uses very less resources.
ad_da
- 芯片ad0809与da0832的实现程序-ad0809 chip with the realization procedures da0832
CRC16_VHDL
- CRC16 VHDL component implements sequential algorithm for incoming data CRC16 calculation
flash222
- 通过USB控制FLASH自动加载FPGA-CONFIG FPGA WITH FLASH
Behavioral-Groestl
- GROESTL hash algoritm implementation on FPGA
clkx_bus
- Imprtant example clk bus for VHDL
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help