资源列表
eeprom_wr
- 本程序是quartus.exe 环境下经过编辑和仿真之后的eeprom中的i2C 通讯协议的驱动程序-This program is quartus.exe edited and simulation environment after the eeprom in the protocol driver i2C
serial_VHDL
- FPGA进行串口通信的程序 VHDL编写的 -FPGA for serial communication procedure prepared by the VHDL
rc4
- RC4算法，WEP算法，加解密，密钥长度256-RC4 algorithm, WEP algorithm, encryption and decryption
DDS
- 主要现实FPGA中TLV5618模块，学习将模拟电流信号转化为数字信号，并且显示到数码管，本程序范围0-5V-TLV5618 major reality in the FPGA module, learning the analog current signal into a digital signal, and the digital display, the program range 0-5V
DE1_i2sound
- Good vhdl code for WM8731
FPGA_UART
- FPGA串口通信，比较好的实现串口通信。对于串口通信研究有帮助-FPGA serial communication, serial communication better. Help for serial communication research
dead
- PWM波形的取反，以及死区的设置。验证程序是正确的。-PWM waveform inversion, and the dead zone settings. Verification process is correct.
Verilog
- 用verilog实现的电子日历程序,在Quartus II上编译通过-Implemented using verilog electronic calendar program, compiled by the Quartus II
stopwatch
- Stop watch code in verilog
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
BlockRAM
- xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
cordic_exer
- 自己编写的CORDIC文件，总共6层，收敛于y轴，即求平方根和正切函数-the cordic verilog HDL file made by myself