资源列表
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- 简单cpu设计 -包括内存单元,运算单元,数据及模块同步单元,状态机单元-CPU design- include memory module, alu module, synchronization module(data and block), finite state machine module
32niosiiprogram
- 32位nios ii处理器用于对RSA加密模块进行数据传送与处理-Nios ii processor 32-bit RSA encryption module used for data transmission and processing
choose_vhdl
- 用于二选一电路,利用IF语句,简单好用,十分方便,希望能有所帮助,谢谢.
Digital-display
- 数码管显示实现代码 共阳极显示 从0-F十六进制显示-Digital display implementation code Common anode display From 0-F hexadecimal display
hc595
- This source code implement led module using 74HC595
fashenqi(shunxu)
- Verilog 这个程序是一个关于顺序形成的发生器,希望大家多多批评指正,可用之人能够用得到-Verilog This program is a sequential formation generator, and hope a lot of criticism and the person available to get
LCD_Top
- FPGA 的verilog LCD显示代码-FPGA code in verilog LCD display
nn_last
- Neural Network with FPGA and VHDL codes + Matlab model
uart_mod
- 与上位机通信的串口驱动程序,基于VHDL语言-uart module
clock
- fpga clock 设计,资料较好,供大家参考,非商用目的哦
8bitclk_div
- 任意整数分频计,verilog编写,仿真通过-Any integer frequency meter
PLL
- FPGA板上的锁存器PLL控制代码(verilog代码)-FPGA board latch the PLL control code (Verilog code)
