资源列表
10_100M-Ethernet-
- 10M 100M 以太网 Verilog 源代码-10M 100M Ethernet
OR1200-Voice
- 基于EP3C开发板的采用OR1200 CPU的语音回放系统-Voice playback system based on OR1200
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- VHDL出租车计费器设计，课程设计完美通过优秀,各个功能模块讲解十分清楚-Taxi meter VHDL design, curriculum design the perfect through outstanding
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- VHDL出租车计费器设计，课程设计完美通过优秀,文档内容是该课程设计的论文，里面详细介绍了该设计的实现和各个模块的具体实现细节，这是河南科技大学课程设计内容-Taxi meter VHDL design, curriculum design the perfect through the excellent content of the document is that the curriculum design papers, which detailed the specific imple
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- VHDL出租车计费器设计论文文档，word格式，内容详细，介绍完整，功能强大。-Taxi meter VHDL design paper documents, word format, detailed descr iption complete and powerful.
ALU
- Verilog编写的ALU，可实现数学、移位、逻辑运算-ALU Verilog prepared, enabling mathematics, shift, logical operations
counter
- Verilog语言编写的8进制同步、异步加法计数器-Verilog language octal synchronous, asynchronous addition counter
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
bits
- verilog语言，移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
freq
- verilog 编写的频率计 管脚绑定支持Xilinx Spartan6-verilog prepared frequency meter pin binding support Xilinx Spartan6
sata_phy_latest.tar
- 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
szz
- 基于CPLD的数字钟，用VHDL语言编写，数码管显示，可调时调分，具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.