资源列表
szz
- 基于VHDL语言编写的EDA程序，可试小时分秒的自动进位，也可手动调时。-Based on Automatic carry EDA VHDL language program, you can try hour, minute and second, you can manually adjust the time.
X16
- 基于VHDL语言编写的EDA程序，可显示“北华航天”四个字，也可尽享扫平，也可手动调结。-Based on EDA VHDL language program, you can display North China Aerospace words, but also enjoy the swinger, it can also be manually adjusted knot.
pinlv
- 基于VHDL语言编写的EDA程序，用数码管显示，频率大小。数字精确到0.1 -Based on EDA VHDL language program, with a digital display, frequency size. Digital precision to 0.1
mul
- vhdh code for modified multiplier in advanced mathematics
dds
- 这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
UART_proj
- 串口发送接受功能，上位机发送消息给FPGA，FPGA接收后将相同的消息发送至上位机。-A serial port to send in function, PC sends a message to the FPGA, FPGA after receiving the same message is sent first place machine.
at2402_iic
- FPGA通过IIC协议，与外部eeprom存储器at24c02进行数据存储，并取出数据显示的功能-The FPGA through the IIC agreement, at24c02 block with external eeprom memory for data storage, and remove the data display function
IIC
- 基于FPGA开发板的IIC读写实验源代码，可以直接使用-FPGA-based development board IIC reading test source code can be used directly
LCD1602
- 基于FPGA 的1602显示源代码，可以直接使用-FPGA based 1602 show source code can be used directly
xapp220
- xapp220对应的pdf文档，gold码和LSFR在无线中的应用-LFSRs as Functional Blocks in Wireless Applications
USBRead
- FPGA+USB通信程序VerilogHDL代码-the code of FPGA+USB communication in verilogHDL
fp
- Verilog分频仿真结合蜂鸣器程序例程，以及仿真测试脚本程序Tastbench.-Verilog simulation combined with buzzer divide routine, and simulation test scr ipt Tastbench.