资源列表
StopWatch
- Verilog 编写的 秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
verilog
- 用verilog写的代码，已经过调试，可以试用一下。-Verilog code used to write, has been testing, you can try.
spartan_alu_8_bit
- Verilog based 8 bit ALU module, implemented on Spartan 3E FPGA.
verilog_golden_reference_guide
- verilog_golden_reference_guide 经典verilog教程。-verilog tutorial verilog_golden_reference_guide classic.
dram_cntl
- DRAM Controller verilog file
sdram32
- DDR SDRAM source verilog source codes
zlg_avalon_lcd128_64
- 基于avalon的12864液晶模块ip核-The 12864-based LCD module avalon nuclear ip
fulladder4
- VHDL图形文件实现的4位全加器，希望对大家有用！-VHDL graphics files to achieve four full adder, in the hope that useful!
vhd2vl
- VHDL to verilog converter
Vhdl1
- Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below wo
fir-vhdl-code
- FIR FILTER CODE with VHDL