资源列表
cam
- This Verilog desription shows an example for a Content Adressable Memory (CAM)
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
divide_by_3
- This module divides the input clock frequency by 3.
I2C_receiver
- 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
asynchronoussignal
- 描述跨时钟域分析,分析和解决异步时钟同步设计问题.-Descr iption of cross-clock domain analysis, analyze and solve design problems in asynchronous clock synchronization.
cymometer
- 数字频率计的源码 最大测量频率达到30MHz-Digital frequency meter measuring frequency of the source code to achieve the maximum 30MHz
gh_vhdl_lib_3_47
- Opencores的VHDL元件库3.47版-The VHDL component library Opencores version 3.47
traffic
- 交通灯 vhdl 进程
gh_timer_8254_1_1
- opencores的8254vhdl源代码，只需修改总线接口即可使用-8254vhdl the opencores source code, just modified to use bus interface
undistort
- floating point arthematic function with verilog code
ps2_verilog
- 用Quartus II 7.2 开发的ps2键盘与计算机串口通讯的程序-Quartus II 7.2 with the development of the ps2 keyboard and the computer serial port communication program