资源列表
Altera_timing
- 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
juzhenjianpan
- 矩阵键盘应用于FPGA的verilog代码，使用的是DE0，引脚已分配-Matrix keyboard used in the FPGA verilog code, using DE0, pin has been assigned
SINADA
- DE2开发板配套的AD/DA子板的驱动程序。-DE2 development board supporting the AD/DA daughter board drivers.
count_16
- 16位计数器-16-bit counter
xiayuwen
- verilogHDL语言学习的相关资料，非常好用，还有夏宇闻的课件学verilog的应该都知道夏老师的-Language Learning verilogHDL relevant information, very easy to use, as well as courseware Xia Xue Wen verilog should all know the summer of teachers
Freq
- 这是一个频率计的程序代码，能检测信号的频率，已生成IP核，能直接在软件上仿真运行。-This is a frequency meter program code, can detect frequency signal generated IP core that can run directly on the simulation software.
gold_code
- Gold code project with VHDL files
DualPortRAM
- 此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
fft
- the zip file includes the material including vhdl coding basics. these will be very helpful to a basic programmer.
Nios
- Altera公司开发的用于其FPGA的的Nios软核入门介绍
LIP6431CORE_NTSC_Video_Decoder
- NTSC Video Decoder Verilog Source code
Multiplier_quartus-II8.0
- 在quartus II8.0中实现乘法器，进过仿真验证过的，没有问题。-In quartus II8.0 realization in on time-multiplier, entered the simulation validated, no problem.