资源列表
xilinxxapp623decouplingcaps
- Xilinx - Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors
keshengsheji
- 基于altera公司的cycloneIII的课程设计，主要功能是选手抢答，有倒计时功能，一名选手抢答后其他人无法抢答，倒计时同时停止，若没人抢答，则倒计时归位。-altera company cycloneIII curriculum design based on main function is to answer the players, there is a countdown, after a player who was unable to answer other answer,
285
- 用FPGA的IO口来控制频率器件hmc704m(Using FPGA to control frequency devices hmc704)
基于Verilog的基础CPU
- 一个可以进行abs(a+b-c)的CPU，包含仿真代码，完全一步一步进行，具体到细节
colorbar
- VGA在800*600分辨率屏上显示竖型彩条10份，扫描时钟是通过例化IP核PLL_CLK进行分频得到40MHz-VGA color display type vertical strip 10 parts, scan clock by instantiating the IP core PLL_CLK performed on 800* 600 resolution screen frequency to be 40MHz
verilogvga
- 基础的VGA显示代码，VERILOG语言编写-Based VGA display code, Verilog language
LED
- xilinx V6板卡上的根据时钟的LED流水灯程序，包括chipscope的时序提取模块，已在在V6上验证通过-xilinx V6 under the clock on the board LED light water procedures, including the timing chipscope extraction module has been verified through on the V6
Encoder
- 一个简单的编码器设计，提供给广大初学者参考。-A simple encoder design, available to the general reference for beginners.
clock-design-verilog-Fpga
- verilog设计的计时表，数字电路设计，FPGA-using verilog design watch, digital circuit design, FPGA
基于FPGA的软件CDR
- 用FPGA实现CDR，可用于LVDS串化解串，ALTERA原厂工程，实用！
calculator-project-VHDL-FPGA
- Calculator PROJECT FPGA ALTERA DE-2
C20_sram_vga
- FPGA应用如sd卡控制，led控制，vga音频控制-Sd card FPGA applications such as control, led control, vga audio control