资源列表
i2c_slave
- I2C interface slave tape out verification ok
if_3w
- 3-wire interface slave tape out verification ok
CPU
- 简易CPU设计 利用VHDL编写。包含一个可以用于检验的LPM-RAM-DQ-CPU-design VHDL
SPWM
- 基于simulink下的SPWM仿真可以看出脉冲电压电流波形，并且通过FFT进行谐波分析-As can be seen based SPWM pulse voltage and current waveforms under simulink simulation and harmonic analysis by FFT
FIR
- 用VHDL写的FIR滤波器，前端有DDS产生波源-Write VHDL FIR filter, front end DDS generated wave source
ShanYu
- 改程序为删余程序，它可以实现3/4,2/3的删余功能，并且通过QUARTUS II 软件编译。-Change the procedure for puncturing procedure, which can be achieved punctured 3/4, 2/3 of the function, and by QUARTUS II software compiler.
verilog-0.9.7.tar
- iverilog 0.9.7源码文件，Verilog转换工具-iverilog 0.9.7
NIOSII
- 用NoisII软核实现超声波测距的时序和485通信-Soft-core with NoisII timing and realization of ultrasonic distance measurement 485
anjian2
- EP2C35F系列开发板关于机械按键的消抖实验，测试，仿真代码-EP2C35F Series development board on key debounce mechanical experiments, testing, simulation code
LGFXY
- EP2C35F系列开发板关于简易逻辑分析仪的设计，仿真，使用外置ADC芯片-EP2C35F Series development board on simple logic analyzer design, simulation, use an external ADC chip
szxszw
- 数字钟（4位）的显示计时现显示和带全置位功能的非常完善的时钟设计，设计层次清晰-Digital clock (4) the timing of the display and will now be displayed with full set of clock function very well designed, clear design hierarchy
uart_verilog.tar
- 在FPGA上实验UART的verilog源码,可综合,已测试OK.-The experimental UART on FPGA verilog source