资源列表
ccd_timing
- tcd1209d drive-timing
clockprj
- vhdl实现的万年历代码，年月日 星期 闹钟功能、-vhdl to calendar code, date week alarm clock function,
work
- 数字系统设计及VHDL课上用的易于混淆的代码-Digital system design and use of the VHDL code lesson is easy to confuse
LCD_Display_kb
- This VHDL Code express how can you connect an LCD To FPGA Spartan 3ee
1_traffic_light
- 交通灯verilog代码， 包括测试代码。-Traffic lights verilog code
FIFO
- FIFO，先进先出缓冲器，verilog源代码，包括测试代码。-FIFO, FIFO buffer, verilog source code, including test code.
LIFO
- LIFO，先进后出缓冲器（栈），verilog源代码，包括测试代码。-LIFO, last-out buffer (stack), verilog source code, including test code.
ALU
- ALU，两种类型的verilog源代码，包括测试代码，原创。-ALU, two types of verilog source code, including test code, originality.
32FIRVHDL
- 基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 -32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
pid-vhdl
- 基于vhdl的pid控制器设计，可以用quartus等软件实现。数字控制系统pid设计源代码。-Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co
FPGA--FIR--bishe
- 一篇参考的毕业设计论文，做的是参数可调的数字滤波器。有详细的原理介绍，设计源程序及仿真流程与结果-A reference of the graduation design paper, adjustable parameters of digital filter. Have detailed introduces, the principle of the design source program and the simulation process and result
efuse_ctrl
- E-fuse controller for TSMC 0.16um