资源列表
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
eightscaleEDAdesign
- 基于FPGA的电子琴,用VHDL实现,完成八个音阶的输出-FPGA—based organ，with the realization of VHDL，complete the eight scale output.
ide
- ide 的HDL描述.有接口和时续-HDL descr iption of the ide. when there is interface and continued
Example-s2-1
- 其中的EPLL、MY_DQ和MY_DQS模块是用Altera的IP产生器MegaWizard产生的-EPLL MY_DQ MY_DQS
FHT_example
- Altera FPGACPLD FHT_example design
source
- ModelSim对Altera设计进行功能仿真的简单操作步骤-modelsim simulation
Project
- 熟悉Altera IP的产生和实现方法定制一个8B10B编码器- 8B10B codeer
Project
- 定制一个双端口RAM，DualPortRAM-RAM，DualPortRAM
uart_regs
- uart_regs core目录下为Altera的IP宏功能模块-Altera IP uart_regs core
dds
- 利用EDA硬件描述语言来实现DDS功能，利用VC++6.0实现sinx,cosx数据的采集，用quart2软件为载体实现-The use of EDA hardware descr iption language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
MultiplicadorSHIF
- This code creates a 8 bit full multiplier.
FiltroDSP
- This sources implement a 8-bit FIR Filter with selectable coefficent rom.