资源列表
m8
- 这是一个8分频的VHDL语言设计程序，也可以看成是8进制计数器-This is an 8-frequency design process of the VHDL language can also be seen as a hexadecimal counter 8
compare4
- 这是一个4位比较器的程序，利用VHDL语言运用在FPGA等硬件上-failed to translate
DECODER
- decoder3_8实现了FPGA或CPLD 实现3-8译码器的功能-decoder3_8 to achieve the realization of the FPGA or CPLD decoder functions 3-8
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
4m
- 使用VHDL语言产生4M分频，用于描述硬件功能-4M generated using the VHDL language frequency, used to describe the hardware features
EDA-basedtechnologiessuchasprecisionmulti-function
- 在对三种测频方法进行分析的基础上，介绍了基于EDA技术的等精度测频原理。给出采用AT89C51实现控制并通过FPGA来设计多功能等精度数字频率计的具体方法。该频率计可以兼顾频率计对速度、资源和测频精度等各方面的优化需求。-Frequency of three methods of analysis based on EDA technology based on the principle of frequency measurement accuracy, etc.. AT89C51 give
lift
- 我自己写的六层电梯程序，用的语言是VHDL，还有仿真的图，非常有用，-I wrote it myself six lift procedures, the language used is VHDL, simulation of the Fig also, very useful,
VerilogHDL
- 一些很有用的verilog源码 希望对大家有帮助- some very useful source of Verilog， I hope it is helpful to all of us 。
miaobiao
- 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
dongtaishumaguan
- 用verilog HDL编写的基于fpga的动态数码管显示程序。-Verilog HDL prepared with fpga based digital control of dynamic display program.
Upload
- Hello Everyone, this site provides useful document to students like me those who are starts doing project in Programming field.
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- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of