资源列表
lcd_i80_verilog.tar
- 在FPGA上通过i80(intel 8080)接口驱动LCD的verilog源码.-In the FPGA i80 (intel 8080) interface to the LCD driver verilog source.
Multiply8-6
- FPGA verilog用移位相加的方式来实现8位的乘法器-FPGA verilog With shift and add a way to achieve 8 multiplier
LED_SCAN1
- FPGA 四位数码管的动态显示-数码管动态扫描模块-Dynamic FPGA four digital tube display- digital dynamic scanning module
datapath
- 单片机PIC16C5X的datapath代码，包括ALU,alu_mux,w_reg和各个指令的代码-The datapath PIC16C5X microcontroller code, including ALU, alu_mux, w_reg and each instruction code
MRAM2012
- STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确-STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct
PIC10
- microchip公司PIC16C5X的各个模块的verilog代码，包括代码实现，英文手册和国外参考资料文献-verilog code microchip company PIC16C5X each module, including the code, and foreign reference manuals in English literature
barrelshifter
- barrel shifter of 32bit using mux2by1.It is implemented in 5stages of mux.
black_jack
- verilog编写的21点游戏，用状态机写的，A可以表示1也可以表示11.-verilog 21-point game, written by a state machine
circuit_timing
- verilog延时电路的不同写法，和综合能否。可对比学习-Different wording verilog delay circuit, and comprehensive ability. Comparable learning
shift_reg
- 移位寄存器，实现了16位移位寄存器的功能，基本原理可以供大家参考-Shift registers to achieve a 16-bit shift register function, the basic principles for your reference
TLB
- 用verilog语言实现了快速线性列表的查找，程序实现了一个基本框架，下载下来可以添加新内容-Using verilog language to achieve a fast linear list to find the program implements a basic framework, you can add new content downloaded
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.