资源列表
lcd1602
- 艾米电子的液晶1602的Verilog语言程序 -Amy e-LCD 1602 of the Verilog language program
priorityencoder
- priority encoder program coding
lcd-counter
- a counter implementation on lcd for spartan 3e board
vhdl
- VHDL实验 7段数码管译码器设计与实现-VHDL experiments 7-segment LED decoder design and implementation
liushuidengyouyi
- 此程序是用vhdl语言描写的流水灯程序，功能是流水灯左移-This procedure is used in light water vhdl language to describe the program, the function is left light water
h264invtransform
- H.264 inverse transform in VHDL
IODELY
- Xilinx IO端口IODELY的使用例程。使用200M作为参考时钟。分别调用两组IODELY完成正向延时和等效逆向延时。-Xilinx IO port IODELY use routines. The use of 200M as a reference clock. Two groups of IODELY positive respectively call completion delay and the equivalent reverse delay.
emmc_cmd_interface_module
- emmc控制芯片CMD命令线主机接口模块,-emmc control chip CMD command line host interface module
AD_SAMPLE_PHASE_MATLAB
- 测试多通道AD同步采集信号的相位差,经过实际项目验证-test multi-channel AD sample signal s phase
1553_module
- MIL-1553B RT controller output shown in BC(RT-BC) VHDL code
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
uart
- 这是一个8位串口收发数据的源码，每个模块都有详细的源码-This is an 8-bit serial data transceiver source, each module has a detailed source