资源列表
Piano
- Simple Piano generator - different frequencyis
compare
- 基于isPLSI1016E_80LJ44芯片简单的十六位比较器-IsPLSI1016E_80LJ44 chip sixteen
ethernet_test
- Verilog implementation of ethernet mac 100mbps test
Verilog-RS232
- 本程序是在FPGA里面模拟RS232串口，并在已调试成功。-This procedure is simulated in FPGA RS232 serial port, and in the debugging success
design
- 状态机描述风格，具有工程价值的状态机结构 源自华为内部-State machine descr iption style, with the value of the state machine structure- Huawei internal
微处理机接口电路设计
- 微处理机接口电路设计，用verilog写-microprocessor interface circuit design, writing Verilog
dac
- Digital to Analog Converter code VHDL
VHDL--8-bit-cpu
- VHDL实现简单的8位cpu功能，该程序代码实现cpu部分功能 -VHDL simple function of the 8-bit cpu
sixuanyi
- 该程序主要是用VHDL编程来实现四选一的电路设计，并可在此基础上修改。-This program is mainly used VHDL programming to achieve one of four selected circuit design, and can be modified on this basis.
LCD-16-x-2
- It is verilog code of lcd 16 x 2.
log_generator
- log10 generator in vhdl. simulated in Modelsim