资源列表
bridge
- FPGA和A/D转换芯片ad7862的IP，可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
Vhdl1
- Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below wo
Src
- 关于nios，可以点亮LED,希望对大家有用。 -About nios, you can light up LED, want to be useful. About nios, you can light up LED, want to be useful.
F00x_PCA0_8Bit_PWM_Output
- 这是关于c8051单片机的PCA的程序，希望大家能够努力的学习这款单片机-This is the chip on the PCA program c8051, hope that we can strive to learn this microcontroller
seg_led_display
- 数码管灯控制程序，动态扫描过程。硬件连接方式比较特殊，位选单独控制，又是级联方式。6个数码管。-Digital tube light control applications, dynamic scanning process. Hardware connection is rather special, separate control of Choice, but also a cascade. 6 digital control.
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
LED-R-G-B-main
- LED R G B三色混合调光PWM控制-LED R G B main
hdl
- ACTEL FPGA 6位数码管计数999999，Verilog描述-ACTEL FPGA 6 bits digital tube count 999999, Verilog descr iption
daima
- VHDL数字时钟而服务而过分为二分给他沃尔夫-VHDL digital clock
VHDL
- VHDL——将100HZ分频成10HZ和1HZ-VHDL- will be divided into 10HZ and 100HZ 1HZ
AD7606
- AD7606的状态机驱动，并口模式，verilog代码，可正常使用。-AD7606 state machine drive, verilog code, can be normal use.