资源列表
booth_mult
- 4*4booth乘法器设计，测试模块，已经通过验证，内有注释，有利于理解booth乘法器原理。-4* 4 booth multiplier design, test module has been validated, there are notes, useful in understanding the booth multiplier principle.
LIBRARY-IEEE
- 将1Mhz的频率信号转换成29hz的频率。分频器-Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider
count_top
- VGA计数，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
chap6
- 小例子,关于Verilog HDL语言的一些小练习,可供初学者进行参考.
LCDTest
- 用VHDL控制LCD1602的源程序，在实际电路中测试通过。
Example2
- this one also verilog source code with its test bench
ask
- 基于CPLD的数字通信系统 ask序列 用VHDL产生 ask序列信号-CPLD-based digital communications system, ask the sequence generated by VHDL signal sequence ask
timeinterrupt
- timeinterrupt 在FPGA上实现定时、计数中断功能-timeinterrupt in the FPGA to achieve timing, counting interrupt function
MMC_SD_interface
- sd card interface in altera kit de2
A8251
- 8251 端口初始化 包含定义13个输入端口和9个输出端口-8251 port initialization definition includes 13 input ports and output ports 9
Desktop
- 用单片机做的LED灯，里面在有几个文件了，如果上传不了，别怪我-Using single-chip LED lights, which in a few files, if you can not upload, do not blame me
shfiting-output-achieved-by-verilog
- 该代码用Verilog语言实现了移位输出功能，主要实现对输入信号进行移位输出，已通过仿真验证。-The code in Verilog realize the shift output function, the main achievement of the input signal shift output has been verified by simulation.