资源列表
asynchoronization_FIFO_design
- 《Verilog HDL 语言编程》 异步FIFO设计（基于Verilog)
__keyBoard
- vhdl编写的4X4键盘扫描程序，可以有效的消除抖动，并且提供蜂鸣器输出。
2fsk
- 基于CPLD的数字通信系统2fsk 用VHDL形成2FSK信号-CPLD-based digital communications system 2fsk signal 2FSK formed with VHDL
fifo8x8
- fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty fifo-fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty
I2C-Master
- I2C Master for Metis to setup MCP4661
c22_FIFO.rar
- 精通verilog HDL语言编程源码之8——异步FIFO设计,Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
fpq
- 用verilog写的各种实用的分频器，很好的参考例子。
EX_CRC
- This example program shows how to send messages between two PICs using CRC error checking.
slavefifo
- FPGA 3D camera experiment
LPC_Peri
- LPC总线中目标机的vhdl代码，Low pins bus-Low pins bus
VHDL
- 2ask vhdl 我感觉是一个很好的程序，供大家参考-2ask vhdl I feel is a good program for your reference
i2c_reader
- 一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。-One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.