资源列表
test4adder
- 用VHDL实现的加法器，可以进行减法运算，运算结果通过数码管显示，由于设计时的按键较少，所以运算的范围比较小，只能计算64以内的加减法运算，可以作为学习资料来参考。-Adder using VHDL implementation can be carried out subtraction, calculation resulted in the adoption of digital tube display, due to the design of the keys relatively
LAB34
- EDA基础_综合实验篇__实验三十四 正弦信号发生器-EDA based on comprehensive test papers _ __ sinusoidal signal generator test 34
keilc51
- keil51 基于C语言的精简单片机教程-keil51 microcontroller based on the streamlined C language tutorial
agx_5v1_01_advanced_copy
- Altera FPGA APEX II,APEX 20K
fpga_example
- EDA技术和VHDL语言实用模块设计，点击驱动，dds，频率计-EDA technology and VHDL functional module design, click the drive, dds, frequency meter, etc.,,,
music_caichawuqu
- 用FPGA驱动蜂鸣器，唱茉莉花这首歌。里面有三个8度音的数据。-FPGA-driven with the buzzer, to sing this song Jasmine. Inside there are three 8-degree sound information.
logmultiplier
- Multiplier based on Logarithm. Completely synthesizable. Tested in spartan 3A DSP series
DE2_USB_API
- FPGA VHDL PROGRAM DE2_USB_API
virtex-5fpgaconfigurationuserguide
- virtex-5 上电加载程序的时序的详细说明，包括bin文件的加载时序-virtex-5 on the power loader timing of the detailed descr iption, including the bin file load timing
rfid_latest.tar
- rfid tag and reader with VHDL for FPGA
VHDLtutorial
- 教你如何快速的熟悉和掌握vhdl语言，了解该语言的逻辑和时序，能尽快的应用到fpga的开发上-Teach you how to quickly become familiar with and master the vhdl language, understand the logic and timing of the language can be applied as soon as possible to the fpga development
dds1
- 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal