资源列表
dianyabiao
- 数字电压表vhdl源程序，一个很不错的东西，欢迎大家有点帮助。-Vhdl source digital voltage meter, a very good thing, welcome to some extent.
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
psk_de
- 应用verilog语言编写实现二元相移键控解调过程。-Application verilog language to achieve binary phase shift keying demodulation.
mdio_slave
- It s VERILOG (not VHDL) code for mdio slave
e1-framer
- e1 framer / de-framer based on itu-t standards state machine using GRAY CODE (or trying to use GRAY CODE
License
- Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license
module-horse
- 跑马灯代码能够让你的LED灯按照你的思路闪烁，基于这种原理可以设计很漂亮的装饰灯。-the horse light can make your led light lits as you thought,it can also design some wonderful lights for decoration based on this priciple.
Dchufaqi
- 用VHDL语言编程来实现D触发器以及它的各个功能。-VHDL language programming to achieve D flip-flop and its various functions.
LPT.rar
- 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据 自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。,The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit config
filter_signed_and_unsigned
- FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
i2c_slave
- I2C interface slave tape out verification ok
da2c
- VHDL硬件描述语言实现DA转化-In quurtus call half adder to achieve 16-bit serial adder