资源列表
digital_clock
- 数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。-Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ct
mips
- 一个单周期流水CPU的实现，其中mips4.vhd是顶层文件-A single cycle CPU
opencores
- opencores开源vhdl的部分代码,从原站cvs下来的最新代码-opencores part of the open source vhdl code, from the original station down the latest cvs code
Generic_Pattern_Detector_3bit
- Generic Pattern detector circuit
RS232Organ1
- 基于FPGA设计的电子琴，VHDL语言和VB开发-FPGA-based keyboard design, VHDL language and VB developers
cpu-design
- 采用VHDL实现的CPU设计代码，工程中包含测试波形。包含CPU设计文档，如指令格式设计和各功能模块说明和指令测试序列，能下载到实验台上直接运行。-CPU design is realized by VHDL Language, the project contains the test waveform. Contains the CPU design documents, such as directives format, instructions for each function mo
huaqiaodaxue---DE2_SD_Card_Audio
- 华侨大学专用实验程序代码，实现sdram播放音乐。 华侨大学eda实验室专用-Chinese University of dedicated experimental program code to achieve sdram play music. Huaqiao University eda laboratory dedicated
DE2_SD_Card_Audio
- 有关于SD卡的音频部分！希望对大家有用！
huaqiaodaxue--DE2_NET
- 华侨大学专用实验程序代码，实现de2网络发送数据包，华侨大学实验室。 华侨大学eda实验室专用-Chinese University of dedicated experimental program code, data packets sent over the network to achieve de2, Huaqiao University laboratory. Huaqiao University eda laboratory dedicated
MAX_II_RevC_brd
- Altera CPLD开发板原理图和PCB -Altera CPLD
beida_verilog
- 这些是北京大学verilog的一些课件，很不错，希望大家能好好学习。-failed to translate
DE2_SD_Card_Audio
- 在DE2实现SD卡音乐播放器 编写语言verilog-In the DE2 SD Card music player to achieve the preparation of language verilog