资源列表
VerilogHDLInterfaceExperiment
- verilog HDL 接口试验源代码，比较实用。
Pk-1k30DEMO
- 几个关于VHDL的几个经典的例子，对于学习VHDL语言和FPGA设计有很大的帮助-Few questions about a few classic examples of VHDL for the VHDL language and FPGA design study of great help
fundamentals-of-digital-logic-with-VHDL-design-so
- Solutions for some common digital design and VHDL programming problems.
top_clock-plus
- 在quartus ii上仿真24小时的时钟在输入基本的时钟信号后，秒数，分数，小时数的变化-After entering the basic clock signal, seconds, fractions, changes in the number of hours of simulation on a 24-hour clock quartus ii
DE2_SD_Card_Audio
- 基于EP2C35F672Ｃ的ＥＤ２实验板自带源文件。DE2_SD_Card_Audio，ＳＤ卡和音频系统的联合操作。-ED2 based on the experimental board comes EP2C35F672C source file. DE2_SD_Card_Audio, SD card, audio system and the joint operation.
MEMORY_CONTROLLER_ASSIGNMENT
- memory controller design in verilog
fpga
- 学习fpga的重要资料-Learn important information on fpga
Multi-function-digital-clock
- 1、 了解数字钟的工作原理。 2、 进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、 掌握VHDL编写中的一些小技巧。 -1, to understand digital clock works. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
key-board-and-mouse-VerilogHDL
- 键盘鼠标的原代码,用FPGA实现,使用VerilogHDL编写-Keyboard and mouse of the original code, FPGA, using VerilogHDL writing
DE2_NET
- 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。DE2_NET，网络模块。-Based on the DE2 board altera company EP2C35672C6 CD in its own file. DE2_NET, network modules.
smallkeybaord
- 用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行
xapp460.zip
- 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）,Video Connectivity Using TMDS I/O in Spartan-3A FPGAs