资源列表
fpga_spi
- 利用FPGA实现SPI接口，与STM32硬件SPI进行联调已成功调试-Using FPGA SPI interface, and the FBI STM32 SPI hardware debugging has been successful
uart_io_test
- verilog实现的uart，在icore2上能测试，代码是特权同学的，我修改了波特率部分。复位部分-verilog achieve uart, on icore2 can test the code is the prerogative of the students, I modified the baud section. Reset section
image-scaling--based-on-the-verilog
- 压缩文件中包含丰富的图像缩放算法，都通过Verilog语言编写的，并包含相应的pdf文件。-Compressed file contains rich image scaling algorithm, written by Verilog language, and contains the corresponding PDF files.
pipeline_cpu
- 1）MIPS架构 2）五级流水线 3）支持MIPS的R,I,J三种指令，一共二十条。 4）内涵PDF教程，工程和激励文件-1) MIPS architecture 2) five line 3) to support the MIPS R, I, J three kinds of instruction, a total of twenty. 4) connotation PDF tutorials, project files and incentives
SPI_slave
- spi的从机模式，实现数据的双向传输，本人用来传输aes数据-spi slave mode
spi
- spi的从机模式，实现数据双向传输，本人用于aes机密模块的数据传输-spi slave mode
dig_clk
- 实现vhdl数字钟 实现时分秒调时 消抖等功能 采用quartus编程实现 -digital clock
costas_DPSK
- 采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz-Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 79
VHDL
- 有一个实际的十字路口设置有东西、南北两个方向的干道,为确保车辆安全通行,在每条干道的每个入口设置了一组两位数码管显示装置和四组红、绿、黄信号灯,分别用来指示东西方向直行、南北方向直行、东西方向转弯和南北方向转弯；同时设有紧急处理状态，数码管显示可有人工控制，并设有初始化功能。-There is a real crossroads to set something, the north-south trunk road in both directions, to ensure the safe
VeriRISC-CPU
- VeriRISC CPU diagram
Blackjack
- Blackjack program VHDL program SystemVerilog
steppulse
- THIS TOUCH SCRREN CONTROLLER IS FOR LARGE SCREEN