资源列表
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
ModelSim-Settings
- 设置ModelSim仿真步骤,运用Quartus II 13.0 (32-bit) University Program VWF 波形文件编程功能后，使用ModelSim-Altera进行仿真。-Set ModelSim simulation steps, using Quartus II 13.0 (32-bit) University Program VWF programming function waveform file, use the ModelSim-Altera simulat
Middlefilter
- 基于FPGA的中指滤波器，使用verilog语言实现，仿真结果正常。-FPGA-based middle filter using verilog language, simulation results properly.
clock
- 数字时钟 LCD1602显示 可以校时。 编译环境QUARTUS II 7.2 -Digital clock LCD1602 display can be corrected. Compilation environment QUARTUS II 7.2
LCD1602-DRIVER(vhdl)
- LCD602的驱动器模块源代码 可直接使用 编译环境QUARTUS II 7.2-LCD602 drive module source code Can be used directly Compilation environment QUARTUS II 7.2
Experiment-of-FPGA_DE2
- fpga开发板DE2的实验讲义，讲解的很详细，可作为入门的学习讲义。-Experiment of FPGA_DE2
sp605_BRD_rdf0033_13.3_c
- SP605调试SFP代码 605的板卡上的芯片是否有ES的尾缀，如果有，请使用CES的。- SP605 SFP test code
ahb_slave_ssrw
- 通过AHB总线简单访问register/RAM 的verilog 子模块 ssrw stands for simple single read write.- submodule used for simple configuration register/RAM accesses ssrw stands for simple single read write.
Verilog-Digital-control
- Verilog HDL数字控制系统设计实-冼进-源代码-4469-Verilog HDL digital control system design implementation- Xian Jin- source code-4469
12jinzhijianfajishuqi
- 同步12进制减法计数器，实现简单的12进制减法计数。-Synchronous binary down counter 12, a simple subtraction of 12 hexadecimal counting.
steppermotor
- 步进电机驱动程序 使用verilog语言，简单易学 留作参考-Stepper motor driver using the Verilog language, easy to learn for reference
ADDA_4CE15
- fpga程序 adda样例 可用于控制adda芯片，verilog-The FPGA program of ADDA sample can be used to control ADDA chip, verilog