资源列表
eth_Management_interface
- FPGA verilog simple MAC 源码-FPGA verilog simple MAC source code
xx_float_add
- 32bit浮点数加法。只实现了两个正数的相加，通过modelsim仿真。开发环境为 Xilinx ISE。-32bit floating point adder. Only realized the sum of two positive numbers through modelsim simulation. Development environment for Xilinx ISE.
chaoshengbo
- 超声波测距单元，在测距完成后在8位数码管上显示测距结果，可用于小车防撞。-Ultrasonic Ranging unit can be used for car crash
phyjingjian
- 通过fpga对phy芯片88e1111进行控制，可改变工作模式，传输速度等。-By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.
rtl
- 通过FPGA对pll进行控制，改变PLL 的输出频率。接口为spi接口。-Pll controlled by FPGA on changing PLL Output frequency. Interface spi interface.
crc
- 一种另类的crc生成办法，改变了流水先结构而使用并行结构。可拓展思路。-An alternative way to generate crc, changing the water first structure to use parallel structures. To develop ideas.
special_crcb
- 一种另类的crc生成办法，改变了流水先结构而使用并行结构。可拓展思路。-An alternative way to generate crc, changing the water first structure to use parallel structures. To develop ideas.
a
- 基于fpga的vhdl十进制 计数器，简单好用-Decimal counter vhdl fpga-based, easy to use
hengwenxiang
- 恒温控制器，由状态机连接到温度传感器，温度控制的控制。该代码是用verilog编写的恒温控制，在每个语句有一个中文的描述-Thermostat controller, controlled by a state machine connected to the temperature sensors, temperature control. The code is written in verilog thermostat control, after each statement has a
clock
- 有防抖模块的双键数字钟，可实现时分秒调节，24小时计时。-There are double anti-shake digital clock module, minutes and seconds can be achieved when the regulation, 24-hour clock.
8bit_multiplier
- 8bit 无符号串联乘法器，由状态机实现，用相加与移位实现乘法功能。-Unsigned 8bit serial multiplier, the state machine implementation, realized by adding the shift multiplication function.
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.