资源列表
fast-crc.tar
- crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture-crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture
adder5
- 5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。-5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
zhuangtaiji
- 用最简单的方法编程写成了一段经典三段式状态机-Three-state machine
can1_model
- DSP2812 and fpga 控制 SJA1-DSP2812 and fpga control procedures SJA1000
amerikan
- This an hours Verilog-This is an hours Verilog
Audio_Demo
- Application of audio in verilog
audio3
- Code to audio in Verilog
FIRAudio
- fı r_audio in verilog
kaynak_kod_FPGA
- CODE TO CCD İ N VERİ LOG
1-D-DWT_verilog-code
- Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The compu
RSA
- 基于FPGA的RSA加解密系统，通过FPGA验证代码为Verilog,开发板为DE2-115-RSA encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115
Twofish
- 基于FPGA的Twofish加解密系统，通过FPGA验证代码为Verilog,开发板为DE2-115-Twofish encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115