资源列表
PID_FPGA
- 这是VHDL实现PID控制算法的源程序，相信会对大家有帮助！-This is the VHDL PID control algorithm source code, I believe everyone will have to help!
clock
- verilog的数字钟代码，在XILINX上运行，可以手动设置时钟、闹钟，可报警-digital clock verilog code running on XILINX, you can manually set the clock, Alarm Clock, alarm
signal-energy-time--test
- 信号到达时间、脉宽检测，能量检测代码，包含tesebench测试文件-The signal arrival time, pulse width detection, energy detection code, including the tesebench test file
www
- 卷积码编码器卷积码是1955年由Elias等人提出的，是一种非常有前途的编码方法 一些资料上可以找到关于分组码的一些介绍-Convolutional code encoder
mimasuo
- 数码管的vhdl源程序，主要用在CPLD或者FPGA上。-it is vhdl language.
iBoard_TFT_Driver_SRC_V1.00
- iboard 4.3寸 480*272 tft CPLD驱动代码 基于verilog 可直接使用STM32 FSMC控制-iboard 4.3 inch 480* 272 tft CPLD driver code based on verilog. it can directly use STM32 FSMC bus control this driver
006
- 华为verilog入门教程 本文主要介绍了Verilog HDL 语言的一些基本知识，目的是使初学者能够迅速掌握HDL 设计方法，初步了解并掌握Verilog HDL语言的基本要素，能够读懂简单的设计代码并能 够进行一些简单设计的 语言的基本要素，能够读懂简单的设计代码并能 够进行一些简单设计的Verilog HDL建模。-Huawei verilog Tutorial This paper describes some basic knowledge of Veril
piaobiao
- 数字跑表，具有复位、暂停、秒表计时等功能。有三个输入端，为时钟输入(clk)、复位(clr)、启动与暂停(pause)。-Digital stopwatch, with reset, pause, stopwatch functions. There are three inputs for clock input (clk), Reset (clr), start and pause (pause).
sin_cic
- 毕设时用Verilog编写的CIC滤波，包含输入正弦信号，-Verilog CIC
MPSK-modulation-VHDL-
- MPSK调制与解调VHDL程序与仿真，本文为DOC文档，附有源码和仿真波形-MPSK modulation and demodulation VHDL program and simulation, this paper for the DOC document, attached to the source code and simulation waveform
elevator-controller-VHDL
- 电梯控制器程序设计与仿真，本文为DOC文档，附有源码和仿真波形-The elevator controller programming and simulation, this paper for the DOC document, attached to the source code and simulation waveform
frequency-measuring-VHDL
- 采用等精度测频原理的频率计程序与仿真，本文为DOC文档，附有源码和仿真波形-Equal precision frequency measuring principle of frequency meter program and simulation, this paper for the DOC document, attached to the source code and simulation waveform