资源列表
MIPs_caculation
- Verilog 实现的32位 定点数运算器-Verilog Number of 32-bit fixed-point arithmetic unit
noise-cancellation
- 脉冲噪声消除 对输入数据循环累加并求平局比较-noise cancellation source code
ISE--Modelsim
- 在ISE工具中使用modelsim进行仿真，并且可用-ISE tools used in the modelsim simulation, and available
ds769_axi_slave_burst
- xilinx AXI4 slave burst 接口的介绍文档，有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
xilinx_DDR3-ctl_code
- VHDL语言，xilinx,ddr3 控制代码，已实现-VHDL xilinx DDR3ctl code
chuzuchejifeiqi
- 能够实验出租车计费系统的描述，下载看完之后-Can describe experimental taxi billing system, finish the download
BasicRSA
- VHDL RSA cypher for FPGA
pipeline-RiSC
- Pipelined RiSC with testbench
single_port_ram
- Single port RAM file VHDL source code
dds
- 可以实现通过串口对DDS进行配置，单音模式，输出频率为50M。已经调试过，直接可以使用-Can be achieved via a serial port configuration of DDS, mono mode, the output frequency is 50 m.Have been debugging, can use directly
MUSIC-FPGA
- altera fpga quartus simulation environment MUSIC algorithm example package with all necessary files including all past year research papers concluded for literature review-altera fpga quartus simulation environment MUSIC algorithm example package wit
FPGA-I2C[Verilog]
- 基于FPGA平台的I2C通信代码 Verilog编写-Based on FPGA platform of I2C communication Verilog code to write