资源列表
lizi
- VHDL的经典实例程序.rar，非常经典-Classic examples of VHDL program. Rar, very classic
10_code_ALTERA7128SLC84
- 10个FPGA实验的源代码，用VHDL编写，是一个试验箱的开发手册-10 CPLD experiment, the source code
counter
- 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
Picking-Bean-Game
- 吃豆子的小游戏,是一个可以控制小球沿路径吃豆子并且成长的游戏，利用时钟分频模块，VHDL语言编写，可以利用VGA模块在显示屏上显示-Pacman game Pacman can control a small ball along the path and growth of the game ........
MIPS-CPU
- 完整的32位MIPS处理器工程，拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
CMMBhardware
- 这是一本关于CMMB的FPGA实现的参考书籍。对编程实现有较强应用价值-This is a book about CMMB, FPGA implementation of the reference books. Have a stronger application of the value of programming
sc_camera_01APR08
- 基于FPGA的CMOS 传感器的图像传输处理.整个设计还基于NIOS.-FPGA-based CMOS sensor Image Transmission. The design is also based on NIOS.
intra4x4
- Intra4x4 in VHDL for H.264 encoder. this module work with 3 intra prediction mode
VCOgen
- Program the ad4360 chip to a specified frequency.
1602led-drive-VHDL
- 使用VHDL编写1602led驱动程序，整个项目文件，可直接使用。-Use VHDL to write 1602led driver, the entire project file, and can be used directly.
KID_ROM
- VHDL实现的只带rom的CISC模型微处理器设计 实现的是输入10个数，输出最小负数-VHDL implementation of the model with only rom the CISC microprocessor designs Realize that the number of input 10 and output the smallest negative
Altera_8051_IPcore_v1.2.rar
- Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5