资源列表
PLL
- 采用Verilog语言，使用IP核的PLL，产生3种不同频率的输出，已测试验证通过-Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
FIFO
- FIFO先进先出控制，调Quartus内核-FIFO IPcore
ifft
- 基于ise软件的ifft编程,包括tb测试文件-the ifft programming of base on ISE software，include tb test file
ad_rx_module
- 基于verilog的串口通信接收部分代码，欢迎下载交流！-Receiving part of the code verilog based serial communication, welcome to download the exchange!
VOIP.tar
- Voice Over IP Phone - implementation in fpga
duotongdao-caiji
- 多通道的数据采集系统，编程规范，值得大家学习labview编程，能运行-Multi-channel data acquisition system, programming specifications, worth learning labview programming, can run
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
DATA_Interleaver
- 这是交织的实现源码 可用于具体的工程实践(This is the interwoven implementation source code that can be used in specific engineering practices)
lcd
- FPGA对液晶屏写控制字，并在液晶屏上显示一个字符串This is a test -FPGA control word written on the LCD screen, and displayed on the LCD screen a string This is a test
fm(912)
- 利用altera的FPGA，采用DDS原理实现FM调试，调试系数可改变，并通过DA变换输出，仿真以及下板测试成功-The use altera FPGA, using the DDS principle to achieve FM debugging, debugging coefficient can be changed through DA conversion output, simulation, and the lower plate test is successful
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
led_display_design_8bitaddr
- 基于FPGA的8位LED自加显示电路，已在Quartus II上进行调试仿真，可在Cyclone IV系列板子上使用-FPGA-based 8-bit LED display circuit Canada, has been debugging simulation on Quartus II, can be used on board Cyclone IV series