资源列表
Divider
- VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
EMP1270
- vhdl spi通讯十分好用，可以对AD7634进行spi通讯！-vhdl spi comment
iic_func
- 驱动EEPROM （24LC32）。单字读写代码-Drive EEPROM (24LC32). Single word read and write code
DMA
- VHDL code of DMA controller
motor
- this file is vhdl code of motor
URAT
- URAT的VHDL设计及时序仿真、调试、测试。含有波形图
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
mul8x8
- 8位无符号数与8位无符号数的乘法的VHDL源代码
Printer
- The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .-The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .
adder
- adder subtractor porgramme
la_usb-SPISRAM
- 有关到SRAM的VHDL程序,也涉及到USB接口，希望对大家有所帮助
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.