资源列表
fulladder
- 由数字电路知识可知，一位全加器可由两个一位半加器与一个或门构成，其原理图如图1所示。该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路；最后将全加器电路编译下载到实验箱，其中ain,bin,cin信号可采用实验箱上SW0,SW1,SW2键作为输入，并将输入的信号连接到红色LED管LEDR0,LEDR1,LEDR2上便于观察，sum,cout信号采用绿色发光二极管LEDG0,LEDG1来显示。 图1.1 全加器原理图-it s a
filter
- 滤波器，经过modelsim仿真得到了正确的结果-Filter through modelsim simulation get the correct result
ch2ex
- 部分电路模块的VHDL代码，包括组合逻辑与时序逻辑电路-Part of the circuit module VHDL code, including combinational logic and sequential logic circuit
ddr
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
SRAM
- VerilogHDL语言读写SRAM内部数据。SRAM芯片型号为61WV102416ALL，即1024K字，每字16位，共16Mb。工作在100MHz频率下。-VerilogHDL language to read and write internal data SRAM. SRAM chip model 61WV102416ALL, ie 1024K words, each word 16, a total of 16Mb. Work in the 100MHz frequency.
uart
- 状态机实现的可配置uart模块，经过fpga验证-State machine implementation can be configured to uart module, after verification fpga
key3_key4
- 基于CPLD带延时消抖的3*4矩阵键盘程序-Debounce delay of CPLD-based band of 3* 4 matrix keyboard program
par_bak
- 本程序旨在完成 并口 sram 232串口的通信实验 作者亲测可以使用。程序设计到两个时钟及多进程通讯和单进程状态机的基础模块。-This program is designed to complete the parallel port SRAM 232 serial communication experiment of pro-test you can use. Programming to the basic module of the clock and multi-process c
dianzichen
- 应用VHDL语言编写的电子秤程序，并且使用压力传感器-Applications written in VHDL, electronic scale program, and use the pressure sensor
qiangdaqi
- 四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.
cordic verilog 求sin cos的源程序
- cordic. it's about how to calculate sin and cos with the FPGA!
dianti
- 一个vhdl语言写的描述六层电梯的运行，有报警信号。通过了测试