资源列表
freq_high2low
- 输入一个高频时钟，输出一个频率可设置的周期信号的verlog模块，在系统设计时很方便-Enter a high-frequency clock, the output frequency can be set up a periodic signal verlog modules, system design at a very convenient
v91SysGen
- audio program in spartan6 FPGA
pre_norm_addsub
- 一种用VHDL语言描述的浮点前规格化的源代码编程-VHDL language used to describe a floating-point before the standardized programming source code
mac_snist
- wire less mac layer implementation using vhdl
multiplier
- 8*8的乘法器，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
uart
- uart veilog源码 含有testbench-uart verilog
watchdog.tar
- verilog编写的watchdog代码!请参考！
multiplier
- 32位乘以32位乘法器，由datapath 和控制中心组成，输出64位结果-32bits by 32 bits multiplier
test1
- 4位数字频率计的verilog HDL设计，精度比较准的-4-digit Cymometer verilog HDL design, the accuracy of the quasi-comparison
Ds18b20_bin2bcd
- DS18B20数字温度计中小数部分转换BCD码-DS18B20 digital thermometer small number of parts to convert BCD code
mimasuo
- 用VHDL编写的数字密码锁,很实用，喜欢请下载
led-flow
- led霹雳游侠灯，超炫，教你不用PWM发生器也能实现霹雳灯的设计-Knight Rider led lights, stunning, you do not teach PWM generator can be designed to achieve thunderbolt lights