资源列表
Sainty2
- 里边有一个半加器。、一个全加器、一个触发器和一个无符号4乘4的乘法器程序，可以完成4位无符号数相乘-Inside there is a half adder. , A full adder, a flip-flop, and an unsigned 4 by 4 multiplier process can be completed by multiplying the number of 4-bit unsigned
QPSK_peng
- OFDM的QPSK调制与解调,有说明，有需要的朋友可以-OFDM QPSK modulation and demodulation, a note, a friend in need can look
fpga_pid
- 在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立-PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors
uart_vhdl
- 异步通信接口包括测试文件，有三个模块组成-Asynchronous communication interfaces, including the test file, there are three modules
verilog
- verilog HDL 入门学习的源代码。 包括双向语法，计数器，状态机，锁存器，uart等-Introduction to learning verilog HDL source code. Including two-way grammar, counters, state machines, latches, uart, etc.
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
drusrc
- 通过arm下载fpga程序。已经成功通过测试-Download fpga program through the arm. Has been successfully tested
aes
- AES is a code encryptioin function after RC5.
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
i2c
- 用I2C读写并在数码管上显示，已调试过，尽可下载-test read and write with I2C
SCHK
- 实验图1是一含计数使能、异步复位和计数值并行预置功能4位加法计数器，例1是其VHDL描述。由实验图1所示，图中间是4位锁存器；rst是异步清信号，高电平有效；clk是锁存信号；-Figure 1 is a test with count enable, asynchronous reset and preset features include numerical parallel adder four counters, Example 1 is described in VHDL. By e
3P3_wimdow
- 图像插值算法，窗口为3*3,用于图像的除去死点，以及提高清晰度或者使图像柔和-3*3 window