资源列表
ANALYSIS-OF-FULL-ADDER
- DEscr iptION OF FULL ADDER
EQctrl_20b_edge
- verilog edge type DFE
AdcMem
- -- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcMem -- Purpose: Clock crossing data buffer made from distributed memory. -- Tools: -- Limitations: none--- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcMem
scr
- 高级篇03：基于matlab和fpga的FIR滤波器设计-Senior chapter 03: matlab and fpga based FIR filter design
boxing
- 波形产生器：用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure
dpmem2clk.tar
- Dual port memory VHDL/Verilog design
RAM-Image
- SRAM_Image to manage one line
DDSverilogsource
- DDS的VERILOG原代码，请大家多支持
ROM
- FPGA ROM利用FPGA实现的ROM只能认为器件处于用户状态时具备ROM功能。使用时不必要刻意划分，而ROM单元的初始化则是设计人员必须面对的问题。-FPGA ROM
flash_read_and_write
- 适用于满足I2C协议的flash读/写操作程序，只需要设置要读/写的字节数，就可以直接使用！
CONFIG_REG
- this files describe how to configure an ADV7180this files describe how to configure an ADV7180
bcd
- 4位bcd码加法器的verilog代码 -4 bit bcdadder verilog4 bit bcdadder verilog