资源列表
speak
- 扬声器：利用VHDL编写程序实现发声报警功能-Speaker: the use of VHDL programming to achieve audible alarm
verilog-project
- its matlab live video streaming code
RISC
- RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
dianti
- FPGA的电梯控制程序，用vhdl语言实现电梯的控制的代码-FPGA elevator control program, using vhdl language implementation code for the control of the elevator
linear-code
- 线性分组码的matlab 源程序 线性分组码的verilog源程序-linear code matlab/verilog
fenpinqi
- 用Verilog语言写的三分频电路所需要的代码-Written in third with Verilog code required frequency circuit
simple-16-bitvhdl-cpu
- central processing unit for processor using vhdl
cordic23
- CORDIC算法的文件 还有测试文件 经测试可用-The CORDIC algorithm file also test files used by the test
pwm
- 采用VHDL编写的步进电机控制程序。运行200步后停止-Prepared using VHDL stepper motor control program. After running 200 steps to stop
microcont
- 数字时钟设计基于FPGA的数字存储示波器的设计 doc基于FPGA的数字存储示波器的设计 122 基于... 基于单片机的车载时钟控制系统研究 doc基于单片机的车载时钟控制系统研究-microcontroller-based digital clock, set the time, stopwatch, alarm set
dcm100
- ADC12D800 source code
three_division_VHDL_programe
- 根据上面思想写的三分频程序,1/3和50％占空比的程序.