资源列表
CU-RAM-CODES
- CU RAM VHDL codes for spartan 3E board
create_new_component
- sopc 中，新建component。详细介绍了如何根据HDL代码生成黑盒的过程。-SOPC, the new component. Described in detail how the HDL code generation black-box process.
AsynCommCtrl
- 基于VHDL的串行异步通信电路的设计 包括串行发送器，异步接收器，以及控制器 vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
JDL12864LCD
- 基于Actel A3P030 FPGA，液晶采用JDL12864串行接口，时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
degital-clock
- 基于FPGA 编写的数字钟程序，分为 时计时器，分秒计时器，选择器和译码器 4个模块-degital clock
XC9536XL
- 通用FPGA CPLD下载电缆的XC9536XL编译程序
CPLD_AD_AVR
- CPLD程序，程序中实现了PWM波的产生、ADS8364并行高速AD的读写控制，与AVR单片机的通信控制。CPLD以类似外部RAM的方式被AVR读写，AVR单片机只需要向固定的地址写入或者读取即可。 本程序对高速数据采集系统有很好的参考作用，可以以此修改为其他应用场合。-The CPLD program, the program to achieve a PWM wave generation high-speed AD ADS8364 parallel read and write con
DDR2PTiming
- 用Xilinx ip core 生成器所产生的DDR2控制器，进行时序分析代码-Xilinx ip core generator a ddr2 controllor time analysis
spreadspectrum5
- these files are written in verilog but i am uploading in text format
PS2
- CPLD 上实现 PS2键盘协议，可以读取PS2键盘，然后用串口发送，CPLD为Altera的EPM240-CPLD to achieve PS2 keyboard protocol, you can read the PS2 keyboard, serial port and then send, CPLD for Altera' s EPM240
hostreg_make
- Verilog register creator based on text file input.
pinlvji
- 用vhdl语言写的频率计，可以实现1khz到1Mhz，当低于1Khz时可实现测周期单位为ms，测量精度达到99 ，用数码管动态显示-Vhdl language written with the frequency meter can be achieved 1khz to 1Mhz, when less than 1Khz cycle when unit for detecting ms, 99 accuracy, dynamic display with digital control