资源列表
CANBUS
- 本文包含了CAN的verilog程序及测代码-This article contains the CAN verilog code and testing procedures
I2C
- i2c的通信协议，中英文都有，版本是V2.1-i2c communication protocol, the English have version V2.1
servomat
- antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "ser
Multiple-function-signal-generator
- 基于quartus ii开发环境下的多种函数信号发生器的设计- Multiple function signal generator quartus ii development environment based design
09.数字电压表
- 本实验我们将电位计的阻值转化为模拟值读取出来，然后显示到屏幕上，这也是我们以后完成自己所需的实验功能所必须掌握的实例应用。(In this experiment, we transform the resistance of potentiometer into analogue value and read it to the screen, which is an example application that we must master after we finish the expe
peak
- This code helps to find the peak detection of in receiver system.
UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
cpld_spi
- cpld spi ，功能基本上满足普通项目的使用，欢迎使用。-cpld spi, function essentially to meet the general project use, Welcome.
risc_spm_v14
- 使用Altera CycloneIV 用Verilog语言实现一个精简指令集cpu(Using Altera CycloneIV to implement a streamlined instruction set CPU in Verilog language)
eqingdaqi
- VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
yejing1602
- fpga完成液晶模块的测试功能，效果良好 ，先是清楚-fpga finished LCD module test functions, good effect, first clear
clock
- 闹钟 运用quartus2软件编写程序，具有调整时间，设置闹钟，整点报时等功能，将整个工程打包了-Alarm Clock using quartus2 software programming, adjust the time, set the alarm, the whole point timekeeping function, the whole project package