资源列表
multiplier-experiment
- 周立功Fusion StartKit，fpga开发板的实验例程，恒定系数乘法器实验-The ZLG Fusion StartKit, fpga development board test routines, the constant coefficient multiplier experiment
decoder3_8
- 这是个三八译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder 38, which the program is written in VERILOG, it is suitable for beginners
multiply
- vhdl语言编写，实现了任意位数的两个数的乘法器-Realize any two-digit number of multiplier
verilogCourseware1-13
- 北京大学微电子系verilog课件教程,对初学者很有帮助的
comport
- 接口程序的编写，串并转换。本程序在ISE集成开发环境下编写。适合初学者学习。-Interface program of preparation, string and conversion. The procedures in the preparation of ISE Integrated Development Environment. Suitable for beginners to learn
fpga-vhdl-lcd1602
- fpga 1602测试程序 vhdl语言-fpga 1602测试程序
randomgenerator
- 随机数产生器，能够随机产生两位数，是原理图输入法和vhdl输入方的方法-Random number generator to randomly generated double-digit, is the schematic input and the input side of the way vhdl
JK
- JK触发器的功能实现，采用VHDL编程，可以下载到FPGA中进行演示-JK flip-flop implementation of function, using VHDL programming, you can download a presentation to the FPGA,
FPGA
- FPGA设计高级进阶(清华大学电子工程系)-Senior Advanced FPGA Design (Department of Electronic Engineering, Tsinghua University)
advanced_fpga_qinghua
- FPGA设计高级进阶(清华大学电子工程系)-Advance FPGA design
Day1
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori