资源列表
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
calculator
- 利用verilog和vhdl两种语言写作的计数器，还有个性化设计模块，利用quartusii平台写作。-Use verilog and vhdl counter writing in two languages, as well as personalized design module, using the platform quartusii writing.
Fast-adder-design-using-verilog
- 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
duogongnengdianzizhong
- 具有整点报时功能,整点时响铃5s。具有控制启动和关闭功能。 具有调整起床铃,熄灯铃时间的功能。 具有调整打铃时间长短和间歇时间长短的功能。 -with whole point timekeeping function, the whole point ringing 5s. Have control startup and shutdown functions. Get up with adjustments bell, lights-out bell time function.
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Luces_Secuenciales
- SEQUENTIAL LIGHTS WITH STROBER EFFECT IN VHDL FOR FPGA
uart_regs
- uart_regs core目录下为Altera的IP宏功能模块-Altera IP uart_regs core
4.LED_SHIFT
- xilinx led shift vhdl program
uart_regs
- 串行通讯ip核，经过仿真验证，综合，可以参考使用-Serial communication ip nuclear, through simulation, synthesis, can refer to the use of
fft256
- 利用FPGA ip核实现256点的FFT转换，用vhdL语言实现。-Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
picoblaze07.3.20
- verilog HDL picoblaze07.3.20
ps2
- PS/2 键盘鼠标通信实验。学习PS/2的传输协议，利用实验板上的PS/2接口，实现键盘，鼠标与实验板间的数据通信，并且将从键盘，鼠标接收到的信号解码后通过LCD进行显示。