资源列表
mode3by3_generate_module
- 用verilog编写的3x3模块！用于图像处理算法中的中值滤波和边缘检测等等!-failed to translate
PCtoLCD2002
- 单片机字模软件 单片机字模软件-The chip matrix software chip matrix software chip matrix software
ethmac_latest
- 以太网MAC，已经通过测试，详细说明见内README-Ethernet MAC, has been tested in more detail, see README
FPGA_experience
- FPGA设计经验总结，对你的FPGA设计能力将有很大的提高-The summary of FPGA s design, it will be a great improve to your ability of designing FPGA
FPGA_CPLD
- FPGA/CPLD数字电路设计经验分享,内容包括数字电路设计的一些经验。-Sharing the experience of designing digital circuit with FPGA/CPLD
variableprecision
- variable precisoon multiplier codings
1076_ieee_standard_vhdl_language_reference_manual.
- 1076 ieee standard vhdl language reference manual-1076 ieee standard vhdl language reference manual.pdf
Verilog
- verilog的学习教程，很基础使用，很好的初学者资料-verilog tutorial to learn very basic use, very good information for beginners
frequency_meterd
- 用verilog编写的一个可测1~10mhz的频率计-Verilog write with a measurable 1 ~ 10 MHZ frequency meter
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
1112
- 基于fpga平台的与HMI屏幕的串口连接实现简单图像的显示和触屏操作-Fpga based platform serial connection with HMI screen image display and simple touch-screen operation
clock
- 可以當電子時鐘，有計時、調時還可以設鬧鐘，並且有鬧鈴-When the electronic clock timing, tune while you set the alarm clock and alarm