资源列表
VHDL-language-tutorial
- VHDL语言的语言基础、基本结构，以及常用电路VHDL程序-Language-based VHDL language, the basic structure and common circuit VHDL program
april2010_1
- 基于FPGA的方向滤波指纹图像增强算法实现。目前指纹识别已发展成应用最广泛的一种生物识别技术。-The direction of FPGA-based fingerprint image enhancement filtering algorithms. Currently the most widely used fingerprint recognition has become a kind of biometric technology.
xiaobofilter
- 采用VHDL设计Daubechies 4双通道正交滤波器组，用Quartus II 仿真实现-Daubechies 4 filter group based on VHDL
an_dcfifo_top_restored
- alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。
text5
- 循环彩灯，实现彩灯的花色点亮，利用状态机实现各种花色的实现-Cycle lights, to achieve the suit lit lanterns, using the state machine to achieve the realization of various colors
cpu
- 用verilog描述一个完整的cpu，以完成仿真，仿真结果合理-Complete with a verilog descr iption of the cpu, in order to complete the simulation, the simulation results are reasonable
user-manual-nios-ii
- Instruction manual for nios ii eds.
rdf0028
- Multiboot on Xilinx SP605
ethernet_latest.tar
- ethernet_latest.tar.gz源代码-ethernet_latest.tar.gz source code
DDS
- DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
ethernet_10ge_mac_latest.tar
- The 10GE MAC core is designed for easy integration with proprietary custom logic. It features a POS-L3 like interface for the datapath and a Wishbone compliant interface for management. The core was intentionally designed with a limited feature se
lect-4
- these slides for digital logic design