资源列表
VPR_HET
- 用于学术研究的FPGA布局布线软件VPR
IEEE-VHDL
- IEEE Standard VHDL Language Reference Manual
1076IEEEStandardVHDLLanguageReferenceManual
- IEEE 1076 Standard VHDL Language Reference Manual
motor3_and_motor4
- 程序是CPLD双计数器的程序，主要用于电机编码器计数-Program is CPLD pairs of counter procedures, mainly for motor encoder counts
Frequency_8bit
- 基于FPGA的8位数字频率计，经过本人验证，误差很小，结果通过数码管显示（完整的工程）-8 FPGA-based digital frequency meter, after I verified, the error is very small, the results through the digital display (complete works)
ModelSim6_5_KeyGen
- E:\ModelSim6_5 非常好的材料 -E:\ModelSim6_5 wan neng de
VHDLBasicExperimentSJTU
- 上海交大几个基础VHDL 实验的代码,包括分频器，计数器，七段计数器，状态机，锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
fpga(CAN)
- fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。-fpga CAN Bus Controller source, each with explanatory documents on the use of methods.
radar-controller-design-
- 某个雷达控制器的实现，当中的一些思想还是值得借鉴的，这是哈工大的硕士毕业论文，参考价值很大！-The realization of a radar controller, among some of the ideas or worth learning, This is HIT master' s thesis, a great reference value!
FPGA_AD
- 该资料是在软件无线电中的FPGA的实现的表现，能帮助你更好了解软件无线电-The information is the FPGA s performance in software radio, can help you better understand the software radio
digit_clock
- 1) 计时计数器用24进制计时器电路。 2) 可手动校时，能清零及分别进行时、分、秒的校正。 3) 可整点报时，扬声器发出时长为1s的信号。 4) 可设置闹钟功能。当计时计到预定时间时，扬声器发出闹铃信号，可控制闹铃时长。 -clock
Altera_Audio
- 针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。-The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.