资源列表
StaticPLL
- 介绍FPGA中数字锁相环的设计方法和应用的文档-Introduction of Digital Phase-Locked Loop FPGA design methodology and application documents
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
dds
- 利用EDA硬件描述语言来实现DDS功能，利用VC++6.0实现sinx,cosx数据的采集，用quart2软件为载体实现-The use of EDA hardware descr iption language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
fifo_verilog
- FIFO的verilog实现,内含PDF说明和已建好工程。-Implementation of FIFO using verilog
16b20b
- 以太网16B/20B源代码包括编码器和解码器功能
TLC5615_1-10k
- 进阶实验_13_DA[TLC5615]_2：通过DA输出方波，频率可调，1K~10KHz，步进1K-Advanced experimental _13_DA [TLC5615] _2: By DA output square wave, frequency adjustable, 1K ~ 10KHz, stepping 1K
678_FINAL
- FPGA Implementation of DTC Control Method for the Induction Motor Drive
bin_BCD
- conversor BCD-7SEGMENTOS
fir_16
- 用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
bert
- 误码测试仪，基于FPGA的E1口误码测试仪-BER tester, based on FPGA-E1 port BER tester
cpuyuanma1.rar
- 说明：cpuyuanma1是硬布线控制器源代码， cpuyuanma2是微程序控制器源代码。,Descr iption: cpuyuanma1 hard wiring the controller source code, cpuyuanma2 micro-program controller source code.
uygulama2 grup c
- digital system design example