资源列表
XPS_Custom_IP_Tutorial_3
- Custom IP Core Development tutorial in Xilinx XPS Part 3
Dianzi_Clock
- 基于xilinx的spartan3a平台的电子时钟实现-Based on xilinx s spartan3a platform electronic clock to implement
FPGA
- 关于FPGA的入门教程和软件的使用教程,非常的详细-fpag book
vhdl
- vhdl book for design
alarm
- VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
digital-clock
- 该程序是有verilog实现的fpga的交通灯 适用于cycloneII芯片 可供fpga初学者学习verilog语言时参考，不仅可以显示时钟 还能调整时钟分针秒针-The program is a verilog realize fpga of traffic light is applicable to cycloneII chips available for beginners to learn verilog fpga languages as reference, not only
VHDLDesignMethodnew
- 用VHDL语言实现可编程数字系统设计.该文档说明了VHDL的设计方法,设计单元,举了大量有价值的实例,给出了VHDL的代码.-VHDL language with programmable digital system design. This document describes the VHDL design method, design unit, cited an example of a large number of valuable, given the VHDL code.
UART-LED
- 本实验实现与电脑的串口通讯，并将接收的数据显示在数码管上。-The experimental realization of the computer' s serial communications, and data displayed on the digital receiver tube.
uart_test
- Verilog 基于FPGA的直接RS232串口测试-Verilog FPGA-based test of direct RS232 serial port
counter60
- 基于FPGA的模60计数器，实现0-59计数，四个数码管后两个显示十位和个位，拨盘按钮P11为复位键。-FPGA-based mold 60 counters to achieve 0-59 counts, two of the four digital tube display after ten and a bit, dial button P11 for the reset button.
UART_LED
- 单字节uart收发程序，带led指示,verilog quartusII 12.0 -verilog quartusII 12.0 uart-led
ps2_complex
- 基于verilog的PS口控制程序，比较经典的代码。非常简单-The PS-based verilog port control procedures, more classic code. Very simple. .