资源列表
MyDDR
- 分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
12864lcd_vhdl
- 12864图形点阵液晶驱动vhdl程序，用ise综合-12864 graphics dot-matrix LCD driver VHDL program, and ideally integrated
sdram_control
- sdram控制,完整的sdram读写控制代码，操作简明易懂。带模拟输入，可- sdram control.write and read
RS_FPGA_papers
- 两篇RS编码fpga仿真的硕士论文，看完会对RS编码及其硬件实现步骤有清晰的理解。-2 RS codes fpga simulation master' s thesis, after reading the RS coding and hardware implementation will have a clear understanding of the steps.
Verilog-HDL
- 这是一个FPGA开发的文档,能够帮你在很短的时间里学会FPGA的语言,并带给你很大的帮助,-This is an FPGA development documents, the FPGA language can help you learn in a very short time, and bring you a great help, thank you
count_5
- 5路光栅信号的数字滤波、四倍频、同步锁存、计数-5-way digital filtering raster signal, quadrupled synchronous latch count
AESbyHGY_128
- VHDL描述AES加密系统。加密十次。与完成并可以成功仿真。-VHDL descr iption AES encryption systems. Encryption ten times. And complete and can be successfully simulated.
ddr3_mcb1
- 基于SPARTAN 6 的DDR3的实现。-The Verilog code for DDR3 on the SPARTAN 6
SDRAMPC7YC6008
- 基于cyclone ii系列的FPGA处理USB跟SDRAM通信系统，同时将lcd屏中的数据上传到PC中。-Cyclone ii series FPGA processing USB and SDRAM communication system, and the lcd screen in the data upload to PC.
stratixVGX_5sgxea7_si
- Altera公司的stratixV GX_5sgxea7 系列的原理图和pcb文件，注意，是capture及pdf格式的原理图和allegro格式的PCB文件，稍微修改修改就可以用在您的设计中，让fpga的硬件设计变得简单和高效。-Altera Corporation stratixV GX_5sgxea7 series of schematic and pcb files, note that the capture and pdf format schematic and allegro P
firfilterPfpga
- FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
3.2_TFT_LCD_Datasheet
- ILI9320 + touch datasheets-ILI9320 + touch datasheets....