资源列表
final3
- FPGA实现计算器（四位以内加减乘除，逻辑运算，包含优先级）-FPGA realization of calculator (four less than addition, subtraction, logical operations, including priority)
hls_bluebook
- 非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog-very nice book for catabult study
61IC_S4656
- stm32与FPGA的通讯总线FMSC，非常的实用-stm32 and FPGA communication bus FMSC
DDS
- 实现了基于FPGA的DDS信号源设计，能同时两路输出，输出波形包括正弦波、三角波、方波和锯齿波，且其频率和相位均可调，还能计算两路输出信号的相位差。-FPGA-based implementation of the DDS signal source design, two outputs simultaneously, the output waveforms including sine, triangle, square and sawtooth waves, and its freque
Quartusii
- 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程，对初学者很有帮助。
Counter_Design
- Counter_Design，采用Altera 设计的计数器源码，性能稳定
clock
- VHDL语言，数字钟实现时分秒计数，能够通过按键调整时间-VHDL language, when every minute counts achieve digital clock, the time can be adjusted through the key
FPGA2-4
- 华清远见视频，FPGA入门视频第二讲第4部分-Huaqing vision video, FPGA Introduction Video Part 4 of the second stress
FPGA
- FPGA很不错的入门教学，并有大量实例以帮助学习。-FPGA very good introductory teaching, and there are a lot of examples to help learning.
11
- VHDL出租车计费器设计，课程设计完美通过优秀,各个功能模块讲解十分清楚-Taxi meter VHDL design, curriculum design the perfect through outstanding
plj.FPGA
- 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号，被测方波为信号发生器产生的方波信号，显示电路由TTL芯片及七段数码管组成的电路，自校正输出由CPLD输出已知频率的测试方波信号，可将其输入至测试端口，进行系统精度校正。 -The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac