资源列表
100jinzhijishuqi
- 1） 计数器的时钟输入信号为1S （2）计数器的功能是从0到99计数，以十进制形式显示 （3）有一个复位端clr和两个控制端plus和minus，在这些控制信号的作用下，计数器具有复位、增或减计数、暂停功能。 -1) counter clock input signal for the 1S (2) function of the counter counts from 0 to 99, shown in decimal form (3) has a reset terminal
pickit
- A pickit 2 clone that works fine for me and for others
11_lcd1602
- 本实验是用LCD1602显示英文 显示“HELLO WORLD!”-This experiment is displayed in English with the LCD1602 display " HELLO WORLD!"
VGA_Controller
- sopc中vga control的ip核，可以直接拿来用，保证正确-sopc vga control of the ip in the nucleus, can be directly used to ensure proper
sARM7TM
- ARM7TM core源码，此码来自于opencore组织，此组织免费提供一些IP core，都是一些老外写的。-ARM7TM core source, the code from opencore organizations, this organization provided free IP core, are written by foreigners.
multiplier
- A VHDL program for multiplier, which has been used as a main source for a fir filter
8b10b_encdec
- verilog code for 8b10b
ref_c
- Creat the C code to a hex file for arc4 cpu
camera_bfm
- ov7670摄像头功能总线模型的源代码和源代码仿真-ov7670 camera function bus model source code and source code emulation
23333333345453
- PLD内部锁相环,解决方案,方法介绍,设计思想.-PLD internal phase-locked loop, solutions, methods, the design idea.
state-machine
- 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word
UP3_CLOCK
- 采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。