资源列表
ov7670-1
- ov7670摄像头FPGA数据采集、显示模块，测试可用-ov7670 camera, verilog code, video capture and display
VHDL
- 各种基本的VHDL实例，可以用来参考学习，希望能够帮到大家！-Examples of the basic VHDL can be used to refer to learning, want to help everyone!
dianzhen1616
- 16*16点阵动态滚动显示VHDL四个字母 共有5个模块，4个子模块，top是顶层模块 1.control，产生地址信号，用来读取数据 2.data_store,64组数据，4*16，根据输入地址来输出对应的数据 3.freq，分频模块，由50M主时钟进行分频，得到系统所需的各个频率 4.display,控制点阵模块，将得到的数据进行输出-display VHDL on 16*16 dot matrix
Filterfgfftd
- LIBRARY ieee USE ieee.std_logic_1164.ALL library work use work.fft_pkg.all
dif
- FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates
B_PON_ONU_VHDL
- ATM-PON ONU vhdl proj. file good luck
pl_int
- Zturn board basic board init.
Verilog_example_of_pulse_width_modulation
- 学习verilog的一些资料。是脉宽调制控制的题目，以及源码和仿真文件。感觉代码风格还不错，可以学习一下。-Verilog study some of the information. Pulse width modulation control are the subject, as well as the source code and simulation files. Feel good style of code, you can study about.
Electronic-Clock_1.11
- 用quartusii 设计的电子钟原型文件-Electronic clock with quartusii prototype file design
UART-CPLD
- 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
shuzixiabianpin
- 数字下变频中cic滤波器，级联三级，主要功能是抽取滤波，及重要参考资料，包括数字下变频论文-Digital down conversion of cic filter, cascade three-level main function is to extract the filter, and important reference materials, including digital down conversion papers
Ecar
- 基于FPGA的一个小游戏，在VGA上实现赛车游戏,开发版型号为ANVYL燧石，在Xilinx ISE环境下编译-An FPGA-based games, racing games on the realization VGA, Developer Edition model ANVYL flint, compiled under Xilinx ISE environment